Design of Ultra Low Power CMOS Inverter

Stanford Ultra Low Power CMOS

Stanford has been developing a low voltage CMOS technology which could have a signiicant impact on a wide range of products from personal digital assistants to volume silicon supercomputers. The technology achieves a unique combination of high performance and low energy per operation by combining aggressive voltage scaling with process optimization. The approach is based on the insight that the...

Analysis and design of low power CMOS ultra wideband receiver

Low-Power Adder Design for Nano-Scale CMOS

A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.

Ultra-low-power SRAM design in high variability advanced CMOS

Embedded SRAMs are a critical component in modern digital systems, and their role is preferentially increasing. As a result, SRAMs strongly impact the overall power, performance, and area, and, in order to manage these severely constrained trade-offs, they must be specially designed for target applications. Highly energy-constrained systems (e.g. implantable biomedical devices, multimedia hands...

An ultra-low-voltage ultra-low-power CMOS active mixer

The scaling of CMOS technology has greatly influenced the design of analog and radio-frequency circuits. In particular, as technology advances, due to the use of lower supply voltage the available voltage headroom is decreased. In this paper, after a brief overview of conventional low-power CMOS active mixer structures, we introduce an active mixer structure with sub-mW-level power consumption ...